Hyderabad Chip Firm BITSILICA Grows to 650 Engineers Across Global Hubs

Hyderabad-based semiconductor design company BITSILICA has expanded from a 10-member team in 2019–20 into a global operation of 650 engineers, operating across Hyderabad, Bengaluru, Singapore, Malaysia, Vietnam, and the United States, founder Bhaskar Kakani said.

The firm was established just months before the 2020 lockdown by Kakani, an alumnus of IIIT-H, with a focus on electronic research and development (e-R&D) services. Over the past several years, the company has evolved from assisting global technology firms to supporting domestic design houses and contributing to India’s semiconductor design ecosystem.

As part of its domestic engagements, BITSILICA worked with the Government of India’s "Chips to Startup" initiative, collaborating with universities to build a chip that was showcased by the Prime Minister. The firm also partnered with the central government’s Design Linked Incentive Scheme, architecting a graphics-chip-based System-on-Chip (SoC) to expand its R&D capabilities.

Addressing technical challenges in the semiconductor sector, Kakani noted that typical chip design cycles, known as tape-outs, span 18 months before moving to foundries for manufacturing. A single silicon bug can result in the loss of 18 months of development work and between $100 million and $200 million in investment. Consequently, design programmes require scaling from a core architecture team to 100 or 200 specialized engineers within six to nine months.

The firm’s workload has increasingly tracked the industry’s transition toward artificial intelligence. About 90 percent of the startups BITSILICA engages with are developing chips in the AI accelerator space. Kakani highlighted that traditional CPUs and microprocessors are now taking supporting roles, while GPUs, graphics stream processors, and AI accelerators serve as the primary compute devices.

The company is also navigating rapid shifts in semiconductor process technology, with industry nodes advancing from 7nm to 5nm, 3nm, 2nm, and 14 angstroms over the past five to six years. Kakani stated that the AI computing wave relies on silicon compute capacity alongside High Bandwidth Memory architectures and advancing algorithms.